( preliminary ) 1.8v - 3.3v picotre o tm , 3 - pll, 200mhz, 5 output clock ic 47745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 www.phaselink.com rev 7/2 /07 page 1 features ? designed for pcb space savings with 3 low - power programmable plls and up to 5 clock outputs. ? low - power consumption (< 10 a when pdb is activated ) ? output f requency: o < 133mhz @ 1.8v operation o < 166mhz @ 2.5v operation o < 200mhz @ 3.3v operation ? input frequency: o fundamental c rystal: 10mhz - 50 mhz o reference input: 1mhz - 200mhz ? p rogrammable i/o pin s can be configured as output enable (oe), power down (pdb) input s , configuration select (csel) or clock outputs . ? disabled outputs programmable as hiz or a ctive low ? two distinct configurations selectable with csel (msop - 10l only) ? single 1.8v ~ 3.3v , 10% power supply ? operating temperature range from - 40 ? c to 85 ? c ? available in green /rohs compliant 8 - pin sop or 10 - pin msop packages . description the pl613 - 0 5 is an advanced triple pll design based on phaselink?s picopll tm , world?s smallest programmable clock, technology. this flexible programmable architecture is ideal for high performance, low - power, low - cost applications. when using the power down (pdb) f eature the pl613 - 05 consumes less than 10 a of power , while its configuration select (csel) function allows switching of 2 programmable configurations . besides its small form factor and 3 or 5 outputs that can reduce overall system costs, the pl613 - 05 offer s superior phase noise, jitter and power consumption performance. block diagram
( preliminary ) 1.8v - 3.3v picotre o tm , 3 - pll, 200mhz, 5 output clock ic 47745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 www.phaselink.com rev 7/2 /07 page 2 p l 6 1 3 - 0 5 2 3 4 5 6 7 8 9 clk 4 / csel ^ vdd clk 3 xout clk 0 vdd clk 2 / oem ^ / pdb ^ msop - 10 l 10 1 gnd xin / fin clk 1 pin configuration ^ denotes internal pull up package pin assignment package pin # name msop - 10l s op - 8l type description gnd 1 5 p gnd connection clk 4/ csel 2 - b* - programmable clock (clk4) output or - configuration switching input clk2/oem/ pdb 3 2 b* - programmable clock (clk2) output, or - output enable master (oem) for all clock outputs, or - power d own mode (pdb) input vdd 4, 8 3, 7 p vdd connection clk 3 5 - o programmable clock (clk 3 ) output clk0 6 4 b* programmable clock (clk0) output clk1 7 6 o programmable clock ( clk1 ) output xout 9 8 o crystal output pin. do not connect when using fin xin/ fin 10 1 i crystal o r reference clock input * note : all bidirectional buffers (i/os) incorporate an internal 60k ? p u l l u p r e s i s t o r except when pdb mode is used. in configurations that use pdb, the pdb pin will have a 10m ? pull up resistor. key programming parameters clk[ 0 : 4 ] output frequency output drive strength programmable input/output clk[ 0 ] f vco 2 / p clk [ 1,2 ] f vco x / (p*(1 ,2,4,8 )) or f ref / (p*(1,2,4,8)) clk[3] f vco 2 / (p*(1,2,4,8 )) or f ref / (p*(1,2,4,8)) clk[4] f vco 3 / p or f ref / p where f vco = f ref * m / r m = 11 bit r = 8 bit p = 5 bit (odd/even divider) each output has t hree optional drive strengths to choose from. they are: ? low: 4ma ? std: 8ma (default) ? high:16ma most pins are multi - function i/os and can be configured as: ? oem ? (master oe controlling a ll outputs) ? csel ? (device configuration switching) ? pdb ? (power down) ? clk [0: 4 ] ? (output) ? hiz or active low disabled state p l 6 1 3 - 0 5 1 2 3 4 5 6 7 8 xin / fin vdd clk 0 xout clk 1 gnd vdd clk 2 / oem ^ / pdb ^ sop - 8 l
( preliminary ) 1.8v - 3.3v picotre o tm , 3 - pll, 200mhz, 5 output clock ic 47745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 www.phaselink.com rev 7/2 /07 page 3 functional description the pl613 - 05 is a highly featured, very flexible, advanced triple pll design for high performance, low - powe r applications. the device accept s a low - cost fundamental crystal input of 10m h z to 50 mhz or a reference clock input of 1mhz to 200mhz and is capable of producing 3 (sop - 8l) or 5 (msop - 10l) distinct output fre quencies up to 200mhz. all 3 - plls are fully p rogrammable, with a total of four , 5 - bit p ost vco , odd/even ( patent pending ) ?p - coun ter ? dividers with additional 1, 2, 4 or 8 ?p ost p - counter ? dividers to allow generating the most demanding frequencies easily. the outputs can be programmed to deliver th e generated frequencies from the plls, or the reference input. each bidirectional feature pin ( i/o ) on the pl613 - 05 incorporate s a 60k ? pull up resistor (10m ? for pdb function) and can be configured to perform various functions. usage of various design features of these product s is mentioned in the following paragraphs. pll programming the three plls in pl613 - 05 are fully programmabl e. each pll is equipped with an 8 - bit input frequency divider (r - counter) and an 11 - bit vco frequency feedback loop (m - counter) divider. the three pll outputs are transferred to four 5 - bit post vco , odd/even (patent pending) dividers (p - counter) , as show n in the above diagrams . in addition, there are three optional ( 1, 2, 4 or 8 ) post p - counter dividers , that can further divide the vco frequencies . in general, the pll output frequency is determined by the following formula f out = ( f ref *m) / ( r *p ) for output calculations, please note that ?p? includes the ?p? counter bits plus the additional optional ( 1, 2, 4 or 8 ) dividers, if used. clkx (clock outputs) there are a maximum of 3 (sop - 8l) or 5 (msop - 10l) outputs available on the pl613 - 05 . c lock output frequencies can be configured as follows: clk[ 0 ] f vco 2 / p clk[ 1,2 ] f vco x / (p*(1,2,4,8 )) or f ref / (p*(1,2,4,8)) clk[3] f vco 2 / (p*(1,2,4,8 )) or f ref / (p*(1,2,4,8)) clk[4] f vco 3 / p or f ref / p each output can be programmed with a 4ma, 8ma, or 16ma drive strength . the maximum output frequency is 200mhz @ 3.3v, 166mhz @ 2.5v or 133mhz @ 1.8v. oem (master output enable) one pin can be configured to be a single master oe (oem) input pin that controls all the outputs of the pl6 13 - 05 . in addi tion the state of the disabled outputs can be programmed to float ( hi z ) or active ?0?. the oem pin incorporates a 60k ? p u l l u p resistor for normal operating condition. the logic for oem is shown below: oe m pin oe type (programmable) osc pll output 0 (default) on on hi z 0 1 on on active ?0? 1 normal operation (default) note: typical enable time is 10ns. power - down control (pdb) when activated , pdb ?disables all the plls, the oscillator circuitry, counters, and all other active circuitry. pdb activation disables all outputs and the ic consumes <10a of power. the pdb input incorporates a 1 0 m ? pull up resistor for n ormal o perating condition. the pdb feature can be programmed to allow the output to float (hi z), or to operate in the ?active low? mode. the logic for pdb is shown below: pdb pin pdb type program osc pll output 0 0 (default) off off hi z 1 off off active ?0? 1 normal operation (default) note: typical enable time is < 2 m s.
( preliminary ) 1.8v - 3.3v picotre o tm , 3 - pll, 200mhz, 5 output clock ic 47745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 www.phaselink.com rev 7/2 /07 page 4 on - the - fly configuration switching ( csel ) the pl613 - 05 can be programmed to allow switching between 2 different configurations , allowing for changes in the output frequency and other feature changes. many applications (i.e. video/audio) can use the same design footprint, bu t allow for configuration switching, adher ing to various standards. csel is used to make the switching selection . this pin incorpora te s a 60 k ? p u l l u p r e s i s tor for normal operating condition . the logic for configuration switching of the programmed parts is shown below: csel programmed configuration 0 0 1 1(default) note: typical enable time is 100s . layout recommendation s the following guidelines ar e to assist you with a performance optimized pcb design: signal integrity and termination considerations - keep traces short! - trace = inductor. with a capacitive load this equals ringing! - long trace = transmission line. without proper termination this will cause reflections ( looks like ringing ). - design long traces as ?striplines? or ?microstrips? with defined impedance. - match trace at one side to avoid reflections bouncing back and forth. decoupling and power supply considerations - place d ecoupling capacitors as close as possible to the vdd pin(s) to limit noise from the power supply - multiple vdd pins should be decoupled separately for best performance. - addition of a ferrite bead in series with vdd can help prevent noise from other boar d sources - value of decoupling capacitor is frequency dependant. typical values to use are 0.1 ? f for designs using crystals < 50mhz and 0.01 ? f for designs using crystals > 50mhz.
( preliminary ) 1.8v - 3.3v picotre o tm , 3 - pll, 200mhz, 5 output clock ic 47745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 www.phaselink.com rev 7/2 /07 page 5
( preliminary ) 1.8v - 3.3v picotre o tm , 3 - pll, 200mhz, 5 output clock ic 47745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 www.phaselink.com rev 7/2 /07 page 6 electrical specifications absolute maximum ratings parameters symbol min. max. units supply voltage range v dd - 0.5 4.6 v input voltage range v i - 0.5 v dd +0.5 v output voltage range v o - 0.5 v dd +0.5 v soldering temperature (green package) 260 ? c data retention @ 85 ? c 10 year storage temperature t s - 65 150 ? c ambient operating temperature* - 40 85 ? c exposure of the device under conditions beyond the limits specified by maximum ratings for extended periods may cause permanent damage to the device and affect pr oduct reliability. these conditions represent a stress rating only, and functional operations of the device at these or any other co n ditions above the operational limits noted in this specification is not implied. *operating temperature is guaranteed by design. parts are tested to commercial grade only. ac specifications parameters conditions min. typ. max. units crystal input frequency (xin) fundamental crystal 10 50 mhz @ v dd =3.3v 200 @ v dd =2.5v 166 input (fin) frequency @ v dd =1.8 v 1 133 mhz input (fin) signal amplitude internally ac coupled (high frequency) 0.9 v dd vpp input (fin) signal amplitude internally ac coupled (low frequency) 3.3v < 50mhz, 2.5v < 40mhz, 1.8v < 15mhz 0.1 v dd vpp @ v dd =3.3v 200 @ v dd =2.5v 166 output frequency @ v dd =1.8v 133 mhz settling time at power - up (after v dd increases over 1.62v) 2 ms oe function; ta=25 o c, 15pf load 10 ns output enable time pdb function; ta=25 o c, 15pf load 2 ms vdd sensitivity frequency vs. v dd +/ - 10% - 2 2 ppm output rise time 15pf load, 10/90% v dd , high drive, 3.3v 1.2 1.7 ns output fall time 15pf load, 90/10% v dd , high drive, 3.3v 1.2 1.7 ns duty cycle pll enabled, @ v dd /2 45 50 55 % period jitter, pk - to - pk* (10,000 samples) input 16mhz fundamen tal mode crystal, all outputs at 40mhz, 10pf load, with capacitive decoupling between v dd and gnd. 100 120 ps * note: jitter performance depends on the programming parameters.
( preliminary ) 1.8v - 3.3v picotre o tm , 3 - pll, 200mhz, 5 output clock ic 47745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 www.phaselink.com rev 7/2 /07 page 7 dc specifications parameters symbol conditions min. typ. max. units suppl y current, dynamic, loaded cmos outputs i dd all outputs @ 20mhz 10pf load 15 21 ma supply current, dynamic, loaded cmos outputs i dd all outputs @ 20mhz 10pf load 11 16 ma supply current, dynamic, loaded cmos outputs i dd all outputs @ 20mhz 10pf load 8.5 11 ma s upply current i dd when pdb=0 all outputs @ 20mhz 1 0pf load, v dd = 3.3v <10 a operating voltage v dd 1.62 3.63 v output low voltage v ol i ol = +4ma st d drive 0.4 v output high voltage v oh i oh = - 4ma st d drive v dd ? 0.4 v output curre nt, low drive i osd v ol = 0.4v, v oh = 2.4v 4 ma output current, standard drive i osd v ol = 0.4v, v oh = 2.4v 8 ma output current, high drive i ohd v ol = 0.4v, v oh = 2.4v 16 ma crystal specifications parameters symbol min. typ. max. units fundamental crystal resonator frequency f xin 10 50 mhz crystal loading ra t ing c l (xtal) 15 pf maximum sustainable drive level 100 ? w operating drive level 30 ? w shunt capacitance c0 5.5 pf metal can crystal esr max esr 50 ? shunt capacitance c0 2.5 pf small smd crystal esr max esr 80 ?
( preliminary ) 1.8v - 3.3v picotre o tm , 3 - pll, 200mhz, 5 output clock ic 47745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 www.phaselink.com rev 7/2 /07 page 8 package drawings ( green package compliant) msop - 10l s op - 8l dimension in mm symbol min. max. a 0. 86 1.06 a1 0.05 0. 15 a2 0.81 0.91 b 0.17 0.25 c 0.1 0.2 d 3.00 bsc e 3.00 bsc h -- 5.08 l 0. 43 0. 63 e 0.5 0 bsc dimension in mm symbol min. max. a 1. 35 1.7 5 a1 0.1 0 0. 2 5 a2 1.25 1.50 b 0. 33 0.5 3 c 0.19 0.27 d 4.8 0 5.00 e 3.8 0 4.0 0 h 5.80 6.20 l 0. 40 0.89 e 1.27 bsc c l a 2 e h d a 1 e b a c l a 2 e h d a 1 e b a
( preliminary ) 1.8v - 3.3v picotre o tm , 3 - pll, 200mhz, 5 output clock ic 47745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 www.phaselink.com rev 7/2 /07 page 9 ordering information ( green package compliant) for part ordering, please contact our sales department: 47745 fremont blvd., fremont, ca 94538, usa tel: (510) 492 - 0990 fax: (510) 492 - 0991 part number the order number for this device is a combination of the following: part number, package type and operating temperature range pl613 - 0 5 - xx x x x x * phaselink will assign a unique 3 - digit id code for each approved programmed part number. part number /order number marking ? package option pl613 - 05 - xxx m c j 3 xxx 10 - pin m sop (tube) pl613 - 05 - xxx m c - r j 3 xxx 10 - pin m sop (tape and reel) pl613 - 05 - xxx s c j 3 xxx 8 - pin sop (tube) pl613 - 05 - xxx s c - r j 3 xxx 8 - pin sop (tape and reel) ? note: ?xxx? designates marking identifier that, at times, could be independent of the par t number. please consult your phaselink sales representative for marking informat ion. phaselink corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. the information fu r nished by phaselink is believed to be accurate and reliable. however, phaselink makes no guarantee o r warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. life support policy : phaselink?s products are not authorized for use as critical components in life support devices or systems without the e x press written approval of the president of phaselink corporation. solder reflow profile available at www.phaselink.com/qa/so lderinggreen.pdf part number temperature c=commercial ( 0 ? c t o 70 ? c ) i = industrial ( - 40 ? c to +85 ? c ) package type m=m sop - 10l s = sop - 8l 3 digit id code * (will be assigned at programming time) n one= tube r=t ape and reel
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